Chemical vapor deposition is the process of depositing a solid film on a semiconductor wafer surface through a chemical reaction of a gas mixture. Typically the semiconductor wafer surface or its vicinity is heated in order to provide additional energy to the system to drive the reactions. Chemical vapor deposition can be accomplished utilizing a range of equipment reactor designs, with each reactor design producing slightly different types of film quality. Chemical vapor deposition reactors are broadly categorized based upon the reaction chamber pressure regime used during the operation: atmospheric-pressure (APCVD) reactors and reduced-pressure reactors. The reduced-pressure chemical vapor deposition reactors have two general types. First, there are low-pressure chemical vapor deposition reactors (LPCVD) where the energy input is thermal. Second, there are plasma-assisted chemical vapor deposition reactors, either plasma enhanced (PECVD) or high-density plasma (HDPCVD), where the energy is partially supplied by plasma as well as thermally.
APCVD generally operates in a mass-transport limited regime. At any given time, there may not be sufficient gas molecules present at the wafer surface for a reaction to occur. Therefore, the reactor must be designed to have optimum reactant gas flow to every wafer in the system. APCVD deposited films often exhibit poor step coverage.
LPCVD systems operate at a medium vacuum of about 0.125 Torr, and employ temperatures between 300° C. and 900° C. Conventional oxidation type furnaces (horizontal or vertical) and multichamber cluster tools can be used for LPCVD processing. LPCVD reactors typically operate in a reaction-rate limited regime. In this reduced-pressure regime, the diffusivity of the reacting gas molecules increases so that the mass-transferring of a gas to the wafer no longer limits the rate of the reaction. Because of this transfer state, the gas flow conditions inside the reactor are not important, permitting the reactor design to be optimized for high wafer capacity (e.g., wafers can be closely spaced). Films are uniformly deposited on a large number of wafer surfaces as long as the temperature is tightly controlled. Step coverage is typically good using a LPCVD process.
Yang et al., U.S. Pat. No. 6,406,640, discloses a plasma etching method wherein a dielectric layer such as TEOS is deposited over a BPTEOS layer. The TEOS layer can act to stabilize the BPTEOS layer during processing and/or prevent etching and/or migration of dopants from the BPTEOS layer into a subsequent deposited layer. The capping layer may be etched in a first stage, under optimum etching conditions which are not necessarily the optimum etching conditions for the underlying BPTEOS layer. After the capping layer has been etched, the underlying BPTEOS layer may be etched by an O2 plasma striking method. The plasma striking method includes the use of O2 plasma strike wherein a high concentration of O2, along with CHF3, C2F6 and the like are used first, and after the plasma stabilizes, the O2 concentration is reduced to etch the BPTEOS layer.
Hsuch et al, U.S. Pat. No. 6,489,213, discloses a method for manufacturing a semiconductor device including a BPTEOS layer formed from any of a variety of precursors such as TEOS (tetraethylorthosilicate), TMB (trimethylborate), TMP (trimethylphosphite). The BPTEOS layer may be formed by reacting precursors in a CVD reactor at atmospheric pressure (APCVD) or sub-atmospheric pressure (SACVD), both with the addition of oxygen or ozone. The process is called ozone-PBTEOS or O3-PBTEOS. The BPTEOS layer is typically deposited to a thickness of about 2,000 to about 20,000 angstroms and preferably from about 6,000 to about 15,000 angstroms thick, and may include a dopant concentration that is about 0 to about 6 weight percent boron and about 4 to about 8 weight percent phosphorus.
Wang, et al., U.S. Pat. No. 6,294,483, discloses a method of preventing delamination of APCVD BPSG films. BPSG layers are formed over PECVD silicon oxide layers by atmospheric chemical vapor deposition using ozone and TEOS. The method prevents the formation of voids in deep depression such as are found between metallization lines or closely spaced polysilicon structures in flash memory integrated circuits. Boron and phosphorus BPSG precursors may be used including TMP(trimethyl phosphite) and TMB (trimethyl borate) respectively, and other precursors including TMPO (trimethyl phosphate), diborane, or SiOB.
Huange, et al., U.S. Pat. No. 5,736,450, discloses a process for fabricating cylindrical capacitors for use in DRAMs is described wherein this silicon nitride etch stop layer is eliminated. The silicon nitride etch stop layer is replaced by two dielectric layers that have generally similar properties and other respects but substantially different etch rates. For a fast etching dielectric, O3 TEOS is used while, for the slow etching dielectric, BPTEOS is used. The BPTEOS and the O3 TEOS are etched in 10:1 buffered oxide etch solution (91 percent ammonium fluoride (40 percent strength)) and 9 percent hydrofluoric acid (49 percent strength)).
Ngo, et al. U.S. Pat. No. 6,627,973, discloses a method of fabricating a flash memory semiconductor device having a virtually void-free interlayer dielectric, including the steps of: (a) depositing a first boron-phosphorus-tetraethyl-orthosilicate (BPTEOS) layer on a silicon substrate, the first BPTEOS layer being formed from a group of reagents including a boron dopant, a phosphorus dopant and TEOS, and the depositing step (a) including a first boron dopant flow rate, a first phosphorus dopant flow rate and a first TEOS flow rate; (b) depositing a second BPTEOS layer on the first BPTEOS layer, the second BPTEOS layer being formed from a group of reagents including a boron dopant, a phosphorus dopant and TEOS, and the depositing step (b) including a second boron dopant flow rate, a second phosphorus dopant flow rate, and a second TEOS flow rate.
Mori, U.S. Pat. No. 6,624,020, discloses a method of making a metal oxide semiconductor transistor including providing a semiconductor substrate and forming a trench provided through a silicon nitrite film, a BPTEOS film and a silicon oxide film grown at low temperatures. A native oxide film on the top surface of the BPTEOS film is etched with BHF. Disclosed also is the use of hydrofluoric acid solution to etch the BPTEOS film.
Liu, U.S. Pat. No. 6,248,624, discloses a method of making a semiconductor device including the deposition of alternating layers of doped oxide and non-doped oxide on semiconductor substrates including using TEOS reactant gases that can be doped with boron and phosphorus such that an in-situ doped BPTEOS is used to deposit borophosphosilicate glass films. TEOS reactant gases that are not doped can be used to deposit non-doped oxide layers.
The present invention provides alternatives to the prior art.